{"product_id":"digital-vlsi-chip-design-with-cadence-and-synopsys-cad-tools-neil-weste-9780321547996","title":"Digital VLSI Chip Design with Cadence and Synopsys CAD Tools","description":"\u003cp\u003e\u003ci\u003eDigital VLSI Chip Design with Cadence and Synopsys CAD Tools\u003c\/i\u003e leads students through the complete process of building a ready-to-fabricate CMOS integrated circuit using popular commercial design software. Detailed tutorials include step-by-step instructions and screen shots of tool windows and dialog boxes. This hands-on book is for use in conjunction with a primary textbook on digital VLSI.\u003c\/p\u003e\n\u003ch3\u003eOmschrijving\u003c\/h3\u003e\n\u003cp\u003eDigital VLSI Chip Design with Cadence and Synopsys CAD Tools leads students through the complete process of building a ready-to-fabricate CMOS integrated circuit using popular commercial design software. Detailed tutorials include step-by-step instructions and screen shots of tool windows and dialog boxes. This hands-on book is for use in conjunction with a primary textbook on digital VLSI.\u003c\/p\u003e\n\u003ch3\u003eProductspecificaties\u003c\/h3\u003e\u003cul\u003e\n\u003cli\u003e\n\u003cstrong\u003eAuteur:\u003c\/strong\u003e Neil Weste\u003c\/li\u003e\n\u003cli\u003e\n\u003cstrong\u003eUitgever:\u003c\/strong\u003e Pearson Education (US)\u003c\/li\u003e\n\u003cli\u003e\n\u003cstrong\u003eImprint:\u003c\/strong\u003e Pearson\u003c\/li\u003e\n\u003cli\u003e\n\u003cstrong\u003eVerschijningsdatum:\u003c\/strong\u003e 2009-07-23\u003c\/li\u003e\n\u003cli\u003e\n\u003cstrong\u003eAantal pagina's:\u003c\/strong\u003e 600\u003c\/li\u003e\n\u003cli\u003e\n\u003cstrong\u003eISBN:\u003c\/strong\u003e 9780321547996\u003c\/li\u003e\n\u003cli\u003e\n\u003cstrong\u003eThema:\u003c\/strong\u003e Electronic devices and materials\u003c\/li\u003e\n\u003cli\u003e\n\u003cstrong\u003eBISAC:\u003c\/strong\u003e TECHNOLOGY \u0026amp; ENGINEERING \/ Materials Science \/ Electronic Materials\u003c\/li\u003e\n\u003c\/ul\u003e\n\u003ch3\u003eOver de auteur\u003c\/h3\u003e\n\u003cp\u003e\u003cstrong\u003eProfessor Erik Brunvand\u003c\/strong\u003e is an associate professor in the School of Computing at the University of Utah. He has interests in computer architecture and VLSI systems in general, and self-timed and asynchronous systems in particular. One aspect of his research involves compiling concurrent communicating programs into asynchronous VLSI circuits. The current system allows programs written in a subset of occam, a concurrent message-passing programming language based on CSP, to be automatically compiled into a set of self-timed circuit modules suitable for manufacture as an integrated circuit. He is also interested in investigating the effects of asynchrony on computer systems architecture at a higher level. To explore these ideas he is building a series of prototype asynchronous computer systems out of FPGA and custom VLSI chips.\u003c\/p\u003e","brand":"Intertaal","offers":[{"title":"Default Title","offer_id":56354491433300,"sku":"9780321547996","price":40.99,"currency_code":"EUR","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0967\/0538\/0692\/files\/9780321547996.jpg?v=1783583591","url":"https:\/\/intertaalid.nl\/de\/products\/digital-vlsi-chip-design-with-cadence-and-synopsys-cad-tools-neil-weste-9780321547996","provider":"Intertaal","version":"1.0","type":"link"}